This application relates to a parallel phase locked loop.
In digital signal processing (DSP), a phase-locked-loop (PLL) is commonly used to compensate phase jitter and frequency offset in phase-modulated digital receiver systems, including wireless receivers that use local oscillators to convert a radio frequency (RF) signal to a base-band signal, and optical coherent receivers that use local lasers to facilitate optical signal detection. Due to frequency offset and phase jitter generated at the local oscillator or laser, the received signal often has dynamic phase rotations which must be compensated to recover the original signal. A PLL can track the phase change and frequency difference between the local oscillator/laser and the transmitter, and rotate the phase of received signal to the correct position.
Conventional implementations of PLL require continuous error calculation and tracking of the received signal. Such an approach can be problematic in high-speed applications, such as 10 Gb/s or higher rate digital receivers, because segment-by-segment or parallel processing is needed. However, the inclusion of multiple parallel PLL units can result in sequential inputs to a single PLL unit being discontinuous.